1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device provided with a capacitor. The invention further relates to a method of manufacturing a semiconductor device provided with an interconnection pattern. The present invention still further relates to an apparatus for manufacturing such semiconductor devices.
2. Description of the Background Art
Dynamic Random Access Memories (hereinafter referred to as DRAM) can be classified into several types according to the capacitor structure. One example of the capacitor, a stacked type capacitor, can easily secure a sufficient capacitance even if device elements are miniaturized as a semiconductor device has been highly integrated, since the structure of the stacked type capacitor increases opposing areas of capacitor electrodes. Accordingly, the stacked type capacitor has been widely utilized with higher integration of a semiconductor device.
FIG. 12 is a cross sectional view of a DRAM provided with a conventional stacked type capacitor (hereinafter referred to as first conventional example). With reference to FIG. 12, an isolation oxide film 333 for electrically isolating element regions from each other is formed at a surface of a silicon substrate 331. Under isolation oxide film 333, a channel stopper region 335 is provided. A memory cell of a DRAM is formed at an element region of silicon substrate 331. The memory cell includes one transfer gate transistor 330 and one capacitor 320.
An interlayer insulating film 301 is formed over the entire surface of silicon substrate 331 to cover capacitor 320. A contact hole 301a is provided in interlayer insulating film 301 for exposing a surface of one source/drain region 325. At the one source/drain region 325, a bit line 337 is formed through contact hole 301a. Bit line 337 is formed of a polycrystalline silicon 337a and a tungsten silicide layer 337b. An insulating film 319 is formed over silicon substrate 331 to cover bit line 337.
A problem in the semiconductor memory device shown in FIG. 12 is that patterning in the lithography step is difficult due to a level difference.
A semiconductor memory device illustrated in FIG. 13 is thus proposed in order to solve such a problem.
Referring to FIG. 13, an isolation oxide film 33 is provided at a surface of a silicon substrate 31. A channel stopper region 35 is formed contacting with the lower surface of isolation oxide film 33. A plurality of transfer gate transistors 30 are formed at an element region of silicon substrate 31.
Transfer gate transistor 30 includes a gate oxide film 21, a gate electrode 23, and a pair of source/drain regions 25. An insulating film 27 is formed over silicon substrate 31 to cover a surface of gate electrode 23.
A bit line 37 is connected to one source/drain region 25. An interlayer insulating film 41 is provided over silicon substrate 31 to cover bit line 37 and transfer gate transistors 30.
A contact hole 41a is formed in interlayer insulating film 41 for exposing the other source/drain region 25. A plug layer 43a formed of doped polysilicon, filling contact hole 41a and connected to the other source/drain region 25, is provided on silicon substrate 31. A barrier layer 13 has a triple layer structure including titanium/titanium nitride/titanium. A capacitor 10 is connected to plug layer 43a with barrier layer 13 interposed.
Capacitor 10 is provided with a lower electrode layer 1, a capacitor insulating layer 3 and an upper electrode layer 5.
Barrier layer 13 prevents diffusion of impurities from plug layer 43a formed of doped polysilicon toward lower electrode layer 1, and improves adhesion between interlayer insulating film 41 and lower electrode layer 1.
Lower electrode layer 1 is deposited on a surface of interlayer insulating film 41 to a film thickness of 500 to 700 .ANG. with barrier layer 13 interposed. Lower electrode layer 1 is formed of platinum. On a surface of lower electrode layer 1, capacitor insulating layer 3 formed of highly dielectric material such as tantalum oxide (Ta.sub.2 O.sub.5), plumbous-zirconate-titanate (PZT), plumbous-lanthanum-zirconate-titanate (PLZT), strontium titanic oxide (STO), or barium titanic oxide (BTO) is formed.
PZT and PLZT have the maximum relative dielectric constant when formed on platinum. Therefore, lower electrode layer 1 is preferably formed of platinum.
A sidewall spacer 11a is formed on interlayer insulating film 41 to cover sidewalls of lower electrode layer 1 and capacitor insulating layer 3. Sidewall spacer 11a provides dielectric isolation between lower electrode 1 and upper electrode 5 described below. Upper electrode layer 5 is formed to cover lower electrode layer 1 with capacitor insulating layer 3 and sidewall spacer 11a interposed, thus providing capacitor 10. Upper electrode layer 5 is formed of platinum, doped polysilicon or the like. An insulating film 45 is formed over silicon substrate 31 to cover capacitor 10.
Although the semiconductor device shown in FIG. 13 does not have the problem found in the first conventional example, it has another problem.
The problem will be pointed out in the description of the manufacturing method of the semiconductor device (FIGS. 14 to 23).
Referring to FIG. 14, transfer gate transistor 30 having gate oxide film 21, gate electrode 23 and a pair of source/drain regions 25 is provided on silicon substrate 31. Insulating film 27 covers an outer surface of gate electrode 23. Bit line 37 connected to one source/drain region 25 is formed over silicon substrate 31. Bit line 37 is formed, for example, of doped polysilicon.
A silicon oxide film to be interlayer insulating film 41 is formed by low pressure CVD (Chemical Vapor Deposition) over silicon substrate 31 to cover bit line 37 and transfer gate transistor 30. SOG film (not shown) is applied to a surface of the silicon oxide film in order to planarize the surface. Interlayer insulating film 41 having almost planar surface is provided by etching back the SOG film and the silicon oxide film.
With reference to FIG. 15, a resist pattern 51 having an aperture 51a over one source/drain region 25 is formed on interlayer insulating film 41. Interlayer insulating film 41 is anisotropically etched using resist pattern 51 as a mask. Contact hole 41a for exposing the surface of one source/drain region 25 is formed in interlayer insulating film 41 through etching. Resist pattern 51 is thereafter removed.
Referring to FIG. 16, a doped polysilicon film 43 filling contact hole 41a and contacting one source/drain region 25 is formed over silicon substrate 31. Doped polysilicon film 43 is formed by CVD method to a film thickness of 3000 to 9000 .ANG..
With reference to FIGS. 16 and 17, doped polysilicon film 43 is etched back until at least the surface of interlayer insulating film 41 is exposed. Plug layer 43a filling contact hole 41a and electrically connected to the surface of one source/drain region 25 is provided through this etch back.
Referring to FIG. 18, barrier layer 13 in contact with the surface of plug layer 43a is formed on the surface of interlayer insulating film 41. Barrier layer 13 is formed of triple layers of titanium, titanium nitride and titanium, and each layer is generated one after the other by sputtering method to the thickness of approximately 100 .ANG.. In order to cause reaction between the lowest titanium layer with interlayer insulating film 41 and produce silicide, they are thermally processed in an ambient of nitrogen or argon with a temperature of 650.degree. C. for 20 minutes. A platinum layer 1 is deposited to a film thickness of 500 to 700 .ANG. on barrier layer 13 by CVD. In order to alloy the highest titanium layer constituting barrier layer 13 with the platinum in platinum layer 1, they are thermally processed in an ambient of nitrogen or argon with a temperature of 650.degree. C. for 20 minutes.
With reference to FIG. 19, a highly dielectric material layer 3 formed of highly dielectric material such as PZT is provided on platinum layer 1. If the highly dielectric material is PZT, highly dielectric material layer 3 is deposited to a film thickness of 1000 to 2000 .ANG..
A resist pattern 53 patterned to a desired shape is then formed on the surface of highly dielectric material layer 3.
Referring to FIGS. 19 and 20, highly dielectric material layer 3, platinum layer 1 and barrier layer 13 are successively anisotropically etched using resist pattern 53 as a mask.
A problem found in this step will be described. When the platinum in lower electrode layer 1 is etched, the platinum once removed by etching could attach to sidewalls of lower electrode layer 1, capacitor insulating layer 3 and resist pattern 53 as shown in FIG. 20. With reference to FIGS. 20 and 21, an etching residue 1a contacting the sidewall of lower electrode layer 1 and extending upward is left after resist pattern 53 is removed.
Referring to FIGS. 21 and 22, in the step of removing etching residue 1a by a physical and mechanical method, only the portion of etching residue 1a extending upward from the surface of capacitor insulating layer 3 is removed, and the portion of etching residue 1a below that remains connected to the sidewall of lower electrode layer 1. Referring to FIG. 23, spacer 11a is formed with etching residue 1a left there, then upper electrode layer 5 is formed and capacitor 10 is completed.
Upper electrode layer 5 is formed with remaining etching residue 1a, so that lower electrode layer 1 and upper electrode layer 5 are electrically connected through the remaining etching residue 1a. In spite of the presence of spacer 11a for electrically isolating upper electrode layer 5 and lower electrode layer 1, they are electrically connected with each other. The semiconductor device shown in FIG. 13 having a desired structure (i.e., not having etching residue 1a) cannot be practically obtained. In this case, the function of the capacitor 10 cannot be maintained, and storage and erase operation of a memory cell is impossible.
If etching residue 1a is removed using aqua regia, lower electrode layer 1 would be melted away, causing another problem.